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There are 12 parts to this article:
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Let's jump right in with the schematic(click for insanely large version):
Here is a black and white version. For instructions on how to create this, see this article.
I drew this in XFig. Here is the fig file. I like using XFig, because I can capture pinouts at the same time as I represent the circuit. Tracing wires on the homebrew is quite similar to tracing wires on the schematic. Perhaps the world is different now, but when I first started XFig was the only program capable of handling the complexity of the schematic. Not even Autocad for DOS (12 or so?) could make the fonts and lines correctly, or at least, not easily. Visio actually complained that the circuit was "too complicated", and that I should simplify the drawing.
The insanely large version can be printed landscape and fit to one page. It took a horribly long time to do it in The GIMP, but it did print OK. This was on a 1.7 GHz box with a gig of RAM. I'm not sure what graphics programs can handle this on Windows. The easiest is probably to use XFig with Cygwin. More on that here. For kicks, I did open it on XP with Paint, set the page setup to print to 1 sheet in landscape, and it did a pretty good job.
For an earlier hand drawn version:
Some key points about the schematic:
I buffer the data lines coming off of the Z-80 by putting an inverter between the (2) 74LS244s (BR and BW).
The clock has a 330 ohm pullup resistor. The clock goes directly into the Z-80 clock, but I buffer it with the 5th buffer using the SigB 244 to go out to the PIOs. Many parts of this circuit evolved after the initial breadboard design. I suspect that there was some kind of settling/noise issue that required this. It works now, but I don't know exactly why I didn't run the clock signal from the buffer into the Z-80 clock signal.
The Write Enable switch disables/enables writes to the EEPROM. Nowadays, I'm using EPROMs, but if you are debugging a program and the Z-80 can write to the EEPROM, it is a real drag to re-enter the bootstrap bit-by-bit. The WR output of the Z-80 is inverted, and then run into another NAND gate before it goes on to the three 2816 memories.
There is a S/R flip-flop used to debounce the reset switch on the left side of the 74LS00 (A).
The CS on the BusA 74LS244 is connected to the BUSACK line on the Z-80. I use a front panel and the BUSREQ line on the Z-80 to load the bootstrap program. Since the Z-80 bus is high impedance when BUSACK is low, I set various signals manually this way. Some lines are forced to ground or 5+. I1 and I2 are hooked up to the control panel/display for memory bank select when programming the bootstrap via the front panel.
The PC parallel port interface inverts the signal from the printer on pin 11 (db-25 connector). I put an inverter (74LS00 B) on the output to the PC, which is connected to PIO 2, output A4.
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